Resist patterning techniques employed in the semiconductor lithographic process fundamental to integrated circuit manufacturing usually rely on a fluid dissolution step to remove photoresist polymer either made more soluble or left less resistant to dissolution by selective exposure to some type of photon irradiation or particle bombardment.
It is critically important to control this pattern developing dissolution uniformity carefully to achieve close dimensional control of pattern features, the tolerances of which affect yield and practicable design performance limits of semiconductor devices.
In order to be able to develop uniform photoresist patterns with sub micron geometries, it is necessary to retreat from the current method of developing on a conventional spin developer. Batch immersion developing in a conventional developer is acceptable for some applications, but contamination, uniformity and automation obstacles are not overcome with batch immersion processing. Also, the develop process cannot be accomplished uniformly on very small geometries when developing the wafer pattern side up due to nonuniform developing across the wafer causing critical dimension sizing problems.
Other present develop processes employ fixed developing times which are empirically determined to achieve the desired pattern dimensions, with every attempt being made to hold substrate, resist, and exposing and developing system parameters fixed at optimum values.
Another process used in photoresist removal is to determine the endpoint of the photoresist removal process. Accurate determination of endpoint can provide a basis for automatic adjustment of total development time, which is composed of the time required to initially clear resist in the high solubility areas of the pattern plus predetermined additional development time, for example 50% additional time past end point.
The automatic develop time adjustment can largely compensate, as needed, for patterning process variations in such factors as exposure system intensity and/or timing mechanism, resist thickness, resist sensitivity, substrate reflectance, develop solution effectiveness, developing fluid dispense rate, distribution, temperature, chamber ventilation, substrate spin speed and delay between exposure and development. Monitoring of automatically determined developing times provides an indication of the degree of control being achieved over the various process parameters and any significant drift of developing time can be used to alert technical personnel.
Monitoring changing thickness of transparent films by interpretation of optical interference occurring between film top and substrate reflections of a beam of monochromatic light is a method which has been effectively used in various material subtractive processes in semiconductor fabrication, including resist developing in favorable circumstances.
The effectiveness of optical interference techniques for resist developing end point determination can be seriously degraded by processing considerations sometimes encountered in practice.
In spin/spray developing processes, the spray can disperse the beam, and extraneous optical interference caused by varying developing fluid film thickness overlying the developing resist can also limit signal quantity. Attempts to minimize spray density of fluid film thickness in order to enhance signal quantity can degrade development rate radial and angular uniformity. Low reflectivity of the substrate due to surface texture, transparent film interference integral to the semiconductor substrate, or semitransparent film absorption can reduce signal accuracy. Also a pattern with unfavorable low proportion of the resist area designed for removal present little area changing in thickness such that little signal is obtainable. As the geometries of integrated circuits get smaller, it is more important that all aspects of processing be controlled. Manufacturing process have been based on a "recipe" process, that is, various procedures are followed to produce a desired effect with no regard to what is actually occurring on the semiconductor wafer surface.
The "recipe" method has worked well, but with the requirement for tighter control on wafers with very small geometries, the difficulty of controlling all the variables in a particular process becomes greater.